1. Field of the Invention
The present invention relates to a method of producing bipolar transistors as well as semiconductor devices available for production of bipolar transistors. The present invention is applicable, for instance, to production of semiconductor devices each available as a lateral bipolar transistor and having a bipolar transistor section and a MOS transistor section.
2. Description of the Related Art
In recent years, increasingly larger scale and higher performance semiconductor devices have been demanded, and in association with this tendency the Bi-CMOS LSI having both the advantages of high integrity and low power consumption specific to CMOS and of high processing speed specific to a bipolar transistor (also called BIP hereinafter) is now being watched with keen interest.
Especially in a field where a high performance is demanded, it is required to integrate the most advanced MOS technology with the BIP technology, and so-called the LDD structure is often employed as a preferable MOS structure. In this case, however, sometimes a BIP section may be damaged in reactive ion etching (RIE) of SiO.sub.2 films when forming a spacer for forming the LDD structure. This effect is very remarkable especially in a lateral bipolar transistor because a surface section of the substrate is used as an active area of the device.
Detailed description is made hereinafter for the aforesaid problem with reference to the related art shown in FIG. 1A through FIG. 1D. The semiconductor device shown in these figures has both a lateral bipolar transistor section and a P channel MOS transistor section, and each of these figures is a cross sectional view of an upper section of the silicon substrate illustrating a production process thereof. The related art comprises the following steps (1) to (4).
(1) In a substrate 1, an N.sup.+ -filled up layer 2 and a diffusion layer 3 are formed in the bipolar transistor section. The filled-up layer 2 and the diffusion layer 3 function as a collector output for an NPN transistor (not shown) and a base output for an PNP transistor respectively. Then, after a LOCOS oxide film 4 and a P.sup.+ diffusion layer 5 for device separation are deposited, a gate oxide film 6 is deposited. The thickness of the SiO.sub.2 film is in a range from 400 to 500 as the LOCOS oxide film 4 and in a range from 10 to 20 nm as the gate oxide film 6. Then, openings (indicated by the reference numerals 21, 22) are arranged in the gate oxide film for forming an emitter electrode and a collector electrode for the lateral bipolar transistor section. With this operation, the structure as shown in FIG. 1A is obtained.
(2) A poly-Si film having the thickness from 200 to 400 nm is deposited by means of CVD, N.sup.+ ions are implanted into a gate electrode of the MOS transistor section, P.sup.+ ions are implanted into portions where an emitter electrode and a collector electrode for the lateral bipolar transistor section are formed, and then the aforesaid poly-Si film is processed by using the ordinary dry etching technology leaving a gate electrode for the MOS transistor section and an emitter electrode as well as a collector electrode for the MOS transistor section. With this operation, poly-Si sections 31,32 respectively for emitter and collector electrodes for a bipolar transistor section and a poly-Si section 33 for a gate electrode for a MOS transistor are formed. Then P.sup.- ion implantation is carried out in the MOS transistor section to form an LDD diffusion layer 8. Thus, the construction as shown in FIG. 1B is obtained.
(3) A SiO.sub.2 film having a thickness from 200 to 400 nm is deposited by means of CVD, and a SiO.sub.2 spacer 9 for forming a side wall-shaped LDD by carrying out anisotropic etching by means of dry etching. Then, a side wall 51 is formed also on the poly-Si films 31,32 for electrodes of the bipolar transistor, but in the etching process a base reactive area of the lateral bipolar transistor (indicated by the reference numeral 50) is exposed to over-etching. Then, P.sup.+ ions are implanted into the MOS transistor section to form a source/drain diffusion layer 41. With this operation, the construction as shown in FIG. 1C is obtained.
(4) P.sup.+ ions are diffused from the poly-Si films 31, 32 for emitter and collector electrodes respectively of the lateral bipolar transistor section by carrying out heat processing to form diffusion layers 11,12 for emitter and collector. Then, the source/drain diffusion layer 41 of the MOS section is activated simultaneously. Then, each electrode is formed using the conventional technology for forming a connection layer and the construction as shown in FIG. 1D is obtained. In FIG. 1D, output for the collector, emitter, and base are shown by C,E and B respectively, while output for the source and drain are shown by S and D respectively (The same is applicable in other figures).
However, the following problems exist in the related art as described above. Namely when forming the spacer 9 for forming an LDD as shown in FIG. 1C, the base reactive area 50 of the lateral bipolar transistor is exposed to over-etching. As this section is covered by only the gate oxide film 6 having a thickness from 10 to 20 nm, the surface of the Si substrate 1 is exposed in the aforesaid over-etching process, which causes etching damage. Because of the etching damage, such problems as drop of the Hfe due to increase of the base current and as well as drop of yield due to increase of a leakage current between the emitter and the collector occur.